openhwgroup / cvfpu
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
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Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
OpenTitan: Open source silicon root of trust
VeeR EL2 Core
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
HW Design Collateral for Caliptra RoT IP
Verilator open-source SystemVerilog simulator and lint system
HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
Common SystemVerilog components
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
BaseJump STL: A Standard Template Library for SystemVerilog
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication